1. Field of the Invention
This invention relates to a memory having a configuration of a plurality of bits.
2. Description of Related Art
A pellet check which is a test performed under a wafer state of a semiconductor memory. This test is performed for each of a chips on the wafer by executing a writing operation and a reading operation for data by using a memory tester in the same manner as that of an actual operation.
FIG. 1 is a top plan view for showing one chip of the semiconductor memory comprised of a plurality of bits in the related art. The memory tester has a probe card provided with a plurality of contact needles 3 to be touched to each of terminals 2 of the semiconductor memory 1. Each of the contact needles 3 is connected to each of a power supply terminal, a ground terminal, an address input terminal and a control signal input terminal in addition to input terminals IO.sub.0 to IO.sub.n of the semiconductor memory 1 shown in FIG. 1.
FIG. 2 is a block diagram for showing a configuration of essential parts required for performing the pellet check of the semiconductor memory 1 shown in FIG. 1 of the constitution of the memory tester. This memory tester has a plurality of coaxial lines 5a to 5n, and each one end of the coaxial lines 5a to 5n is connected to each of the contact needles 3 contacted to the input and output terminals IO.sub.5 to IO.sub.n of the semiconductor memory 1. The other ends of the coaxial lines 5a to 5n are connected to the output terminals of each of the drivers 6a to 6n and one input terminal of each of comparators 7a to 7n, respectively. To the other input terminals of the comparators are connected power supplies 8a to 8n for generating a reference voltage. Input terminals of the drivers 6a to 6n are connected to a data generating part 10. The output ends of the comparators 7a to 7n are connected to a discriminating part 11. The data generating part 10 and the discriminating part 11 are connected to a control part 12. In addition, although the memory tester is provided with a power supply voltage generating part or an address generating part or a control signal generating part in addition to the aforesaid configuration, these parts are eliminated for their illustration. Only the required number of coaxial lines 5a to 5n, drivers 6a to 6n and comparators 7a to 7n for performing the pellet check of the semiconductor 1 are illustrated and actually it is possible that a greater number of parts than that shown can be applied.
Operation of the pellet check of the related art using the memory tester shown in FIG. 2 will be described as follows. At first, each of the contact needles 3 of the probe card is touched to its corresponding terminal of the semiconductor memory 1. Then, a predetermined address signal is given to the address input terminal of the semiconductor memory 1 through the contact needle 3 under a control of the control part 12, a control signal is given to the control signal input terminal of the semiconductor memory 1 and concurrently a desired data is generated by the data generating part 10 and given to the input and output terminals IO.sub.0 to IO.sub.n of the semiconductor memory 1 through the drivers 6a to 6n, the coaxial lines 5a to 5n and the contact needles 3 so as to write data into the memory cells in the semiconductor memory 1. Then, the data is read, the electrical potentials of the input and output terminals IO.sub.0 to IO.sub.n of the semiconductor memory 1 are compared with a reference voltage by the comparators 7a to 7n, thereby output data of the semiconductor memory 1 is reproduced and taken into the discriminating part 11. At the discriminating part 11, the written data and the readout data are discriminated for every input and output terminals IO.sub.0 to IO.sub.n so as to discriminate whether the data is normal or not.
In this case, the number of concurrent measurement of chips during the pellet check may be substantially influenced by the number of comparators in the memory tester. In the case of the pellet check in the semiconductor memory of the related art, since the input and output terminals IO.sub.0 to IO.sub.n of the semiconductor memory 1 and the comparators 7a to 7n of the memory tester strictly correspond to each other on a one-by-one basis, there is a problem that if the bit configuration of the semiconductor memory is increased, the number of concurrent measurements is decreased and the measuring cost is increased.